18 years of expertise in SoC Physical Back-End:
CAD-support/PDK: (P-cells, Tech-LEF, OA);
Analog IC Layout, RTL2GDS, Flows and Methodology.
‣ Leading back-end team;
‣ Defining flow, methodologies;
‣ Knowledge-sharing;
‣ Chip-Level Physical Verification (Calibre DRC/LVS) of SoC on GF22FDX technology;
‣ Block-level RTL2GDS design of of blocks for a GF22FDX ASIC (Logic Synthesis with Genus CUI, Place-and-Route, CTS, STA with Innovus CUI, Conformal LEC, Tempus Signoff STA, Calibre DRC/LVS);
‣ European customers support with the flows and methodologies;
‣ Creating flows for new technologies;
‣ Updating flows for existing technologies according to new CAD version requirements;
‣ Knowledge sharing sessions provided to the team.
Power consumption estimation routine was automated and continuos Feedback was provided to the Front-End Team driving optimization of RTL realizations. Keeping The Architect informed we are still withing the Power budget when adding new features.
TSMC28HPC+ based IVA-MMP SoC, containing RISC-V CPU core, Comdiv CPU core, DDR3 controller, High-Speed Serial interfaces (including CSI), PCIe controller and Matrix Processor was succesfully taped-out and functional in Silicon.
Maximum working frequency appeared lower the target, the same time the power consumption was lower the estimation equally both about 20% which can be explained we hit SS deviation of the Proccess and tool pessimism the same time.
Cadence Genus Common UI MMMC flow was implemented to be aware of the Range of TDP possilble together with Switching Activity Annotation to reduce tool pessimism.
TechFile, TechLEF development;
front-end development of new device class – stacked ESD MOSes within 40nm PDK.
Oct 2007 – Aug 2015 • 7 yrs | Moscow, Russia 🇷🇺
Analog layout development on 180nm high voltage technology with
Virtuoso XL, Calibre LVS, DRC, MRC, Tiling.
Achievements: Two successful tapeouts.
Technology Database development and support for Freescale and 3rd-party PDK;
technology LEF development.
Maintain consistency between TechLEF and TechDB.
RTL to GDS Flow development, support and testing.
Achievements:
‣ Deployed Dynamic Abstract capability for Freescale PDKs;
‣ Leaded Encounter Tiling development;
‣ Integrated cadence PVS with the tiling deck from TSMC into Encounter for 28nm and 16nm processes to allow signoff-quality tiling within Encounter and proper timing assessment;
‣ 4 bug CCR for Cadence Encounter and 2 enhancement request CCR for PVS;
‣ Enabled Voltage aware P&R in Cadence Virtuoso and VSR by Voltage-dependent spacing constraints;
Pcell development within PDK team.
Pcell development and testing using Skill language.
PDK Validation (Cadence IC package both cdba & OA, Soc Encounter, QRC, Voltage Storm, Abstract generator, DRD. Mentor Graphics tools (Calibre DRC, LVS, DRV, PEX). Freescale tools)
Communication with colleagues across the globe: PDK Flow Validation team India, customers and developers in US, Israel. Development of new testing tasks, testing flows and methodologies.
Driving automation: enhancement requests for the automation team, self-made scripts.
Ownership of cmos45soi (45nm), cmos32soi (32nm), TSMC's cln40lp (40nm), cln28hp (28nm).
Leadership over intern colleague: help in team integration, lot of training with CAD tools, design flows, methodologies etc.
Leadership over the PDK Validation team during owned PDK's testing: (Creation of Validation Plan, downloading and installing PDK, setting up the environment, tool versions, distribution of the testing tasks across the team, driving meeting the deadline in tight schedule, communication with developers, creating postmortem reports, presentations).
Lead Continuous Validation Improvement program (Analyzing incoming Bug tickets and closure of Validation gaps).
Worked with Physical Verification Team to create DRC and MRC QA cells.
Achievements:
‣ Input quality control done for cmos32soi, cln28hp and cln40lp 3rd party PDKs allowed proper resource assessment and enabled development activities for Freescale internal PDK solutions;
‣ Develop express testing methodology for foundry PDKs;
‣ Technology LEF verification on design IP newsletter creation to present PDK Validation team innovations for the entire company
‣ Expertise in parasitic extraction flow;
‣ Developed LVS-LPE flow for cln40lp technology;
‣ Developed Tiling script for SOC Encounter supplied with Cmos45soi PDK;
‣ Developed SOC Encounter automated flow for PDK testing using shell and TCL scripting allowed to reduce testing time;
‣ Collaboration with design team - performed preliminary DRC assessment of developing IP on cln40lp technology;
‣ Personal “Winning Starts Here” award, Team award for Contribution in the Quality.;
Test flows processing (SOC Encounter, Virtuoso, Assura, PVS, CCO. A variety of tools for IC design automation)
csh and encounter text command scripting (TCL)
Preparation of testcases, writing PCR’s
Achievements:
‣ got familiarity with encounter TCL scripting;
‣ got familiarity with CVS Versioning system;
‣ got ownership over largest test flow in the team;
Digital and analog layout development (Virtuoso layout editor, SOC Encounter); Chip-level SOC design, IO cells layout design, digital cells layout design; Layout verification (Cadence, Mentor Graphics tools DRC, LVS, LPE).
Intel representative in Intel Demo Days activity.
(Common Intel and Microsoft program. Advertisement of released Pentium 4 CPU's together with Microsoft Windows XP OS, leading of demo-stand in large trading centers of 🇷🇺 Moscow).
Responsibilities: provide potential customers with information about Intel innovative CPU's, presentations and technical demonstrations using various software packages. Provide information about features of released OS, propagate information about advantages of the genuine software.
Skills:
‣ Deep knowledge of IBM PC architecture and hardware;
‣ CPU architecture fundamentals;
‣ Practical experience with a number of software applications;
‣ Excellent communication.
👨🏻💻 Vladimir Belyaev
🤙🏻 +44-7961-920002
📪 me@whiteman.ru
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